有关EDA计数器的知识点
1.eda计数器及数码显示设计
带使能端、同步清零端、进位输出端的增一16进制数码管显示计数器-- clk: clock input clr: clear input en : enable input-- ledout: 0-a, 1-b, 2-c, 3-d, 4-e, 5-f, 6-gLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;ENTITY counter2 IS PORT ( clk, clr,en : IN STD_LOGIC; : OUT STD_LOGIC; ledout : OUT STD_LOGIC_VECTOR(6 downto 0));END counter2;ARCHITECTURE a OF counter2 IS SIGNAL cnt : STD_LOGIC_VECTOR(3 downto 0); SIGNAL led : STD_LOGIC_VECTOR(6 downto 0);BEGIN PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF clr = '1' THEN cnt <= (OTHERS => '0'); ELSIF EN = '1' THEN IF cnt = "1111" THEN cnt <= "0000"; ELSE cnt <= cnt + '1'; END IF; END IF; END IF; END PROCESS; co <= '1' WHEN cnt = "1111" ELSE '0'; ledout <= NOT led; with cnt select led<= "1111001" when "0001", --1 "0100100" when "0010", --2 "0110000" when "0011", --3 "0011001" when "0100", --4 "0010010" when "0101", --5 "0000010" when "0110", --6 "1111000" when "0111", --7 "0000000" when "1000", --8 "0010000" when "1001", --9 "0001000" when "1010", --A "0000011" when "1011", --b "1000110" when "1100", --C "0100001" when "1101", --d "0000110" when "1110", --E "0001110" when "1111", --F "1000000" when others; --0END a；功能分析：en为使能端，en为高电平时计数有效，clr为同步清零端，时钟到来时，clr为高电平时清零。
数码管从0显示到F，进位输出为1，然后重新开始计数有问题可以再找我。
2.eda 课程设计 可控计数器的设计
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SHENGHAO ISPORT(CLK:IN STD_LOGIC; SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0); Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END SHENGHAO;ARCHITECTURE SH OF SHENGHAO ISSIGNAL CNT,CNT1:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK)BEGINIF(CLK'EVENT AND CLK='1')THENCASE SEL ISWHEN "000"=>IF(CNT="0100")THEN CNT<="0000"; ELSE CNT<=CNT+1; END IF; Y<=CNT;WHEN "001"=>IF(CNT="1000")THEN CNT<="0000"; ELSE CNT<=CNT+2; END IF; Y<=CNT;WHEN "010"=>IF(CNT="1001")THEN CNT<="0001"; ELSE CNT<=CNT+2; END IF; Y<=CNT;WHEN "011"=>IF(CNT="0001")THEN CNT<="0101"; ELSE CNT<=CNT-1; END IF; Y<=CNT;WHEN "100"=>IF(CNT1="0011")THEN CNT1<="0000"; ELSE CNT1<=CNT1+1; END IF; IF(CNT="1001")THEN CNT<="0000"; ELSE CNT<=CNT+CNT1; END IF; Y<=CNT;WHEN "101"=>IF(CNT="1001")THEN CNT<="0101"; ELSE CNT<=CNT+1; END IF; Y<=CNT;WHEN "110"=>IF(CNT="1000")THEN CNT<="0000"; ELSE CNT<=CNT+2; END IF; Y<=CNT;WHEN "111"=>IF(CNT="0101")THEN CNT<="1001"; ELSE CNT<=CNT-1; END IF; Y<=CNT;WHEN OTHERS=>CNT<="1111";END CASE;END IF;END PROCESS;END SH;。
3.EDA课程设计五进制计数器的VHDL语言设计的源程序
随便编了一个，能通过仿真。
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt5 is port(clk,rst:in std_logic; SEL:in std_logic_vector(1 downto 0); data1_out,data2_out,data3_out:out std_logic_vector(6 downto 0)); end cnt5; architecture arch of cnt5 is signal count:integer range 0 to 9; signal state:std_logic_vector(1 downto 0); begin process(clk,rst) begin if rst='1' then state<="00";data1_out<="1111110";data2_out<="1111110";data3_out<="1111110";count<=0; elsif clk'event and clk='1' then case state is when "00" => data1_out<="1111110";data2_out<="1111110"; if count=4 then count<=0; else count<=count+1;end if; case SEL is when "01" => state<="01";count<=0; when "10" => state<="10";count<=1; when "11" => state<="11";count<=5; when others => null; end case; when "01" => data1_out<="1111110";data2_out<="0110000"; if count=8 then count<=0; else count<=count+2;end if; case SEL is when "00" => state<="00";count<=0; when "10" => state<="10";count<=1; when "11" => state<="11";count<=5; when others => null; end case; when "10" => data1_out<="0110000";data2_out<="1111110"; if count=9 then count<=1; else count<=count+2;end if; case SEL is when "00" => state<="00";count<=0; when "01" => state<="01";count<=0; when "11" => state<="11";count<=5; when others => null; end case; when "11" => data1_out<="0110000";data2_out<="0110000"; if count=1 then count<=5; else count<=count-1;end if; case SEL is when "00" => state<="00";count<=0; when "01" => state<="01";count<=0; when "10" => state<="10";count<=1; when others => null; end case; when others => state <= "00"; end case; case count is when 0 => data3_out<="1111110"; when 1 => data3_out<="0110000"; when 2 => data3_out<="1101101"; when 3 => data3_out<="1111001"; when 4 => data3_out<="0110011"; when 5 => data3_out<="1011011"; when 6 => data3_out<="1011111"; when 7 => data3_out<="1110000"; when 8 => data3_out<="1111111"; when 9 => data3_out<="1111011"; when others => data3_out<="0000000"; end case; end if; end process; end arch;。
4.EDA“可加减计数器”的程序怎么设计
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODE3_8 IS
PORT ( DIN : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
EN : IN STD_LOGIC;
XOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END DECODE3_8;
ARCHITECTURE ONE OF DECODE3_8 IS
BEGIN
PROCESS (DIN, EN)
BEGIN
IF EN = '1' THEN
IF DIN = “111” THEN XOUT
5.EDA,VHDL语言设计：十进制可逆计数器（加减计数器）设计,要
"LIBRARY IEEE;USE IEEE。
STD_LOGIC_1164。 ALL;ENTITY DECODE3_8 IS PORT ( DIN : IN STD_LOGIC_VECTOR (2 DOWNTO 0); EN : IN STD_LOGIC; XOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));END DECODE3_8;ARCHITECTURE ONE OF DECODE3_8 ISBEGIN PROCESS (DIN, EN) BEGIN IF EN = '1' THEN IF DIN = “111” THEN XOUT ELSIF DIN = “110” THEN XOUT ELSIF DIN = “101” THEN XOUT ELSIF DIN = “100” THEN XOUT ELSIF DIN = “011” THEN XOUT ELSIF DIN = “010” THEN XOUT ELSIF DIN = “001” THEN XOUT ELSE XOUT END IF; END PROCESS;END ONE;"。
6.eda怎样用4个2位十进制计数器构成8为十进制计数器
你每个计数器肯定有个时钟信号，对吧，
你只要把第一个2位的计数器的进位位输出，一般式carry位，只要你将它赋给下一个2位计数器的输入时钟就可以了，以此类推
counter_2 c1(.clk(clk);
.cout(cout0);
.. );
counter_2 c2(.clk(cout0);
.cout(cout1)
.. );
counter_2 c3(.clk(cout1);
.cout(cout2)
.. );
counter_2 c4(.clk(cout2);
.cout(cout)
.. );
7.可逆的60进制计数器（EDA,VHDL语言）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODE3_8 IS
PORT ( DIN : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
EN : IN STD_LOGIC;
XOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END DECODE3_8;
ARCHITECTURE ONE OF DECODE3_8 IS
BEGIN
PROCESS (DIN, EN)
BEGIN
IF EN = '1' THEN
IF DIN = “111” THEN XOUT <= “11111110”;
ELSIF DIN = “110” THEN XOUT <= “11111101”;
ELSIF DIN = “101” THEN XOUT <= “11111011”;
ELSIF DIN = “100” THEN XOUT <= “11110111”;
ELSIF DIN = “011” THEN XOUT <= “11101111”;
ELSIF DIN = “010” THEN XOUT <= “11011111”;
ELSIF DIN = “001” THEN XOUT <= “10111111”;
ELSE XOUT <= “11111011”;
END IF;
END PROCESS;
END ONE;
8.EDA“可加减计数器”的程序怎么设计
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECODE3_8 IS PORT ( DIN : IN STD_LOGIC_VECTOR (2 DOWNTO 0); EN : IN STD_LOGIC; XOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));END DECODE3_8;ARCHITECTURE ONE OF DECODE3_8 ISBEGIN PROCESS (DIN, EN) BEGIN IF EN = '1' THEN IF DIN = “111” THEN XOUT <= “11111110”; ELSIF DIN = “110” THEN XOUT <= “11111101”; ELSIF DIN = “101” THEN XOUT <= “11111011”; ELSIF DIN = “100” THEN XOUT <= “11110111”; ELSIF DIN = “011” THEN XOUT <= “11101111”; ELSIF DIN = “010” THEN XOUT <= “11011111”; ELSIF DIN = “001” THEN XOUT <= “10111111”; ELSE XOUT <= “11111011”; END IF; END PROCESS;END ONE;。
9.【eda数字时钟我也是学电子的.能把你的EDA课程设计给我发一份吗
我不是学姐，答案我就不帮你做了，给你一些提示，希望你能独立完成.1：先选对计数器，根据需要选择4位，8位，32位（如果没有32位的计数器可以用2个16位的计数器级联起来，第一级的计数器的高位输出驱动第二级的计数器始终）2:10进制，12进制，60进制的计数器怎么做？你需要一个比较器，比较器输入端比较counter的值和一个preset value，如果两个值相等，则输出一，否则输出0，用这个比较信号来控制counter的复位信号，注意有些复位是低电平有效3：有了上面的这些计数器以后怎么做时钟？用级联的方式把上面这些计数器串联起来，也就是说用function generator 产生一个10Hz的频率分秒的比较器输出当作秒的时钟输入（enable也可以），同样的道理，秒的计数器的比较器出入做分的计数器的十种输入.。